1. Field of the Invention
The present invention relates to a miniaturized capacitor with a solid-state dielectric (MIM or MIS capacitor), as can advantageously be used in particular for integrated semiconductor circuits and preferably for memories, for example dynamic random access memories (DRAMs). Capacitors of this type are known, for example, from U.S. Pat. No. 5,760,434, Published, British Patent Application GB 2 294 591 A, Published, European Patent Application EP 0 553 791 A, IEDM 1998 San Francisco: Y. S. Chun et al. and 1997 Symp. On VLSI Tech. Digest of Tech. Papers: J. M. Drynan et al., pp. 151, 152.
Tantalum oxide (Ta2O5) capacitors have been known for decades. Their high specific capacitance is substantially based on the relatively high dielectric constant and the low thickness of the tantalum oxide dielectric layer. Furthermore, a surface area which is as large as possible is important for a high specific capacitance, in which case, as is known in particular from electrolytic capacitors, an enlarged-area surface, which has been roughened as much as possible, of the electrode is of importance.
MIM/MIS capacitors have already long been used for dynamic random access memories (DRAMs). Capacitors which have a first electrode made from tungsten, a tantalum pentoxide dielectric and a second electrode made from, for example, titanium nitride (TiN) are known from the reference by Drynan et al., 1997, Symposium on VLSI Technology Digest of Technical Papers, pp. 151 to 152. It is also known (EP 0 553 791), in a capacitor with a silicon semiconductor electrode, to produce a roughened surface of the electrode by anodic etching, selective etching, etching with the additional action of UV light, dry etching of silicon or of an amorphous silicon layer or by recrystallization of an amorphous silicon layer which was previously applied (known as the hemispherical graining (HSG) process).
A DRAM capacitor and its fabrication method are known from U.S. Pat. No. 5,760,434. One capacitor electrode, which is referred to as the bottom electrode and is connected to the transistor of the memory cell, in this document consists of TiN. It is in this case a thin film in the form of a cup on silicon oxide which forms the surrounding side wall. The inner wall of the TiN layer, which is of a cup-like shape, is coated with silicon. The silicon is converted into hemispherical grained silicon with the aid of the HSG process, so that the silicon on the TiN substrate which remains unchanged has the known grained structure/structural surface with a surface area which has been enlarged a number of times. This enlarged surface area of the conductive HSG polysilicon forms the electrode surface with is coated with a dielectric. The dielectric is coated with the second electrode (top electrode) to complete the capacitor.
It is accordingly an object of the invention to provide a miniaturized capacitor with a solid-state dielectric, in particular for integrated semiconductor memories, e.g. DRAMs, and a method for fabricating such a capacitor which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which the two electrodes which adjoin the dielectric, in particular the surface of the bottom electrode, consist of an electronically conductive metal with a correspondingly high electrical conductivity, yet nevertheless the electrode surface has a greatly enlarged surface area, as can be achieved with the HSG process for semiconductor materials.
With the foregoing and other objects in view there is provided, in accordance with the invention, a miniaturized capacitor containing a first metal electrode having a predetermined macroscopic form. The first metal electrode has a surface and a region formed of tungsten silicide disposed close to the surface. The first metal electrode has a grown layer containing grained tungsten silicide forming an enlarged surface area disposed on a surface of the region. A solid-state dielectric is disposed on the first metal electrode including the region having the enlarged surface area. A second electrode is disposed on the solid-state dielectric.
The particular features of the present invention can be seen in particular from an advantageous fabrication method according to the invention, which is described below, for the miniaturized solid-state capacitor according to the invention.
For a DRAM capacitor, it is known to provide a form with a macroscopically enlarged surface area for its first (bottom) electrode. By way of example, this may be, as well as the form of a bell or the form of a bore, the form of a column.
Macroscopic forms of this type are sufficiently well known for the relevant capacitors in order to achieve a high capacitance.
In the invention, it is provided that the material of the first electrode, at least in the region below its electrode surface, has an electrical conductivity that is as good as possible. Therefore, according to the invention, either the entire electrode or at least that region of the electrode that is close to the surface is formed of tungsten silicide, which has a good electronic, i.e. metallic, conductivity. For the second case described above, it is alternatively possible, for the invention, to provide polysilicon as the core with a tungsten silicide region which is close to the surface.
According to the invention, the tungsten silicide of the first electrode or at least of its region which is close to the surface contains a stoichiometric excess of silicon. The silicon content may be x=2.0 to 2.5 in the WSix.
A first layer of tungsten silicide which is in this case substoichiometric, for example WSi1.8, with a silicon content of between, for example, 1.5 and 1.9, is applied to the surface of this preferably superstoichiometric tungsten silicide. The thickness of a layer of this type is approximately 10 to 30 nm. A layer of this type can be applied, for example, using known chemical vapor deposition (CVD) processes using, for example, tungsten fluoride (WF6) and, for example, silane.
A further layer of pure silicon, or silicon without any additives, is applied to the first layer, once again, for example, with the aid of a CVD process. This layer is, for example, 10 to 30 nm thick.
The first (bottom) electrode with these two coatings then undergoes a heat treatment at, for example, 800 to 1100xc2x0 C. for from, for example, 1 to 10 sec in an inert atmosphere. During the process step, the material of the substoichiometric first layer changes into at least substantially stoichiometric tungsten silicide WSi2. The invention exploits the fact that, with the process parameters indicated, this transition to stoichiometric tungsten silicide is accompanied by growth of graining. This is grain growth in or at least on the surface of the first layer. The graining of the first layer that occurs results in a significantly enlarged surface area of the electrode surface of the first electrode that is of relevance for the capacitor.
In the method step of the invention that follows, the silicon of the second layer that is still present is etched away down to the first layer, which now has the graining. Consequently, the tungsten silicide surface is completely exposed. It is now recommended to passivate the grained surface of the first electrode. A thermal nitride coating in substantially a single layer, for example with a thickness of less than 1 nm, is suitable for this purpose. The formation of nitride may take place in particular through the action of NH3. The purpose of the passivation is to avoid the formation of any silicon dioxide on the electrode surface. This would in fact considerably reduce the capacitance of the capacitor.
Then, the actual dielectric, for example SiN, of the capacitor according to the invention is applied to the surface of the first electrode which has been fabricated according to the invention and of which the surface area has been enlarged a number of times by the graining achieved. For this application, CVD of SiN from, for example, NH3 and silane is suitable. In addition, it is advantageously possible, in order to reduce the defect density, for the nitride to bexe2x80x94preferably only partiallyxe2x80x94oxidized, so that a thin oxide layer, known as top oxide, is formed. The oxidation to a depth of, for example, up to 1 nm into the SiN dielectric layer leads to saturation of open bonds.
The dielectric which is deposited on the nitride passivation may alternatively also be tantalum pentoxide as a layer applied by a CVD process or an organic tantalum compound or the like which it is known can be used for this purpose. It is recommended for the surface of the tantalum oxide dielectric that has been applied as described above also to be subjected to a heat treatment in an oxygen-containing atmosphere. This measure has the effect of reducing the defect density within the dielectric layer, in particular in the grain boundaries of the dielectric. In this way, it is possible to significantly reduce the leakage current, which represents a drawback for a capacitor.
The pinhole density can also be reduced using these two measures that have been described above for reducing the defect density.
The thickness of the particular dielectric layer is dependent on the dielectric strength required for the capacitor. Although a relatively thick layer reduces the specific capacitance of the capacitor that can be achieved, it increases the dielectric strength of the capacitor. An oxide-equivalent thickness of the layer of between approximately 1 and 5 nm is typical.
The free surface area of the dielectric is covered with the second electrode of the capacitor. The second electrode may consist, for example, of titanium nitride, polysilicon, tungsten, tungsten nitride, tungsten silicide and the like.
In accordance with an added feature of the invention, the first metal electrode has a core formed of polysilicon and the region is disposed on the core.
In accordance with an additional feature of the invention, the solid-state dielectric is a nitride-oxide double layer or is formed of tantalum pentoxide.
In accordance with a further feature of the invention, the second electrode is formed of titanium nitride or tungsten silicide.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a miniaturized capacitor. The method includes the steps of providing an oxide layer having a recess formed therein; fabricating a macroscopically formed body forming part of a first electrode in the recess of the oxide layer, the body having a region formed of tungsten silicide; and coating the region of the body with a layer of substoichiometric tungsten silicide, WSix, with x being between 1.5 and 1.9. A further layer of additive-free silicon is applied to the layer of sustoichiometirc tungsten silicide resulting in a two-layer structure. The body with the two-layer structure is heat treated in an inert atmosphere, until a grained layer substantially formed of the layer of substoichiometric tungsten silicide is formed. The body with the grained layer is coated with a dielectric layer, and a second electrode is formed on the dielectric layer.
In accordance with an added mode of the invention, there is the step of fabricating the body all the way through from the tungsten silicide, WSix, where x=2 to 2.5.
In accordance with an additional mode of the invention, there is the step of fabricating an inner core of the body from polysilicon, the region of body formed from the tungsten silicide is WSix, where x=2 to 2.5 and is disposed on the inner core.
In accordance with a further mode of the invention, there is the step of applying the layer of substoichiometric tungsten silicide at a thickness of between 10 and 30 nm.
In accordance with another mode of the invention, there are the steps of forming the oxide layer on an etch stop layer and the recess formed in the oxide layer continues in the etch stop layer; removing the oxide layer after the body is formed; and applying the layer of substoichiometric tungsten silicide on the body and on the etch stop layer such that, on the body, the layer of substoichiometric tungsten silicide layer is applied at a thickness which is at least twice as that as on the etch stop layer.
In accordance with a further added mode of the invention, there is the step of applying the further layer to a thickness of between 10 and 30 nm and carrying out the heat treating step continuously in an inert atmosphere at 800xc2x0 to 1100xc2x0 C. for from 1 to 10 seconds. The parts of the further layer that remain on the grained layer are removed after the heat treating step.
In accordance with a further additional mode of the invention, there is the step of passivating a surface of the grained layer forming the dielectric layer. The passivation step is performed by thermal nitride coating. In addition, the passivation step can be carried out with a single-layer thickness of less than 1 nm.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a miniaturized capacitor with a solid-state dielectric, in particular for integrated semiconductor memories, e.g. DRAMs, and a method for fabricating such a capacitor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.